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Data Sheet
threshold. The device can be reset by toggling the ON-CLR pin
or by manually pulling the TIMER pin low. On the ADM1170-1 ,
the TIMER pin activates the 2 μA pull-down once the 1.3 V
threshold is reached, and continues to pull down until it reaches
the 0.2 V threshold. At this point, the 100 μA pull-down is
activated and the GATE pin is enabled. The device keeps
retrying in the manner as shown in Figure 35.
The duty cycle of this automatic retry cycle is set to the ratio of
2 μA/60 μA, which approximates 3.8% on. The value of the
timer capacitor determines the on time of this cycle. This time
ADM1170
The ADM1170-2 model has a latch off system whereby when a
current fault is detected, the GATE is switched off after a time
determined by the timer capacitor (see Figure 36 for details).
Toggling the ON-CLR pin, or pulling the TIMER pin to GND
for a brief period, resets this condition.
I RSENSE
5μA
is calculated as follows:
t ON = 1.3 × C TIMER /60 μA
t OFF = 1.1 × C TIMER /2 μA
I RSENSE
2μA
V TIMER
V GSFET
V OUT
60μA
SHORT-
CIRCUIT
EVENT
COMP2
V TIMER
V GSFET
V OUT
60μA
100μA
SHORT-
CIRCUIT
EVENT
Figure 36. ADM1170-2 Latch Off After Overcurrent Fault
SOFT START
The inrush current profile is controlled using an external
capacitor on the soft start (SS) pin. During power on reset, the
SS pin is held at GND. When the pass FET begins to conduct
COMP2
FAULT
COMP1
FAULT
current, a pull-up current source is initiated on the SS pin and
charges the voltage on the soft start capacitor in a linear fashion.
CYCLE CYCLE
Figure 35. ADM1170-1 Automatic Retry During Overcurrent Fault
AUTOMATIC RETRY OR LATCHED OFF
The ADM1170 is available in two models. The ADM1170-1
has an automatic retry system whereby when a current fault is
detected, the FET is shut down after a time determined by the
timer capacitor, and it is switched on again in a controlled con-
tinuous cycle to determine if the fault remains (see Figure 35
for details). The period of this cycle is determined by the timer
capacitor at a duty cycle of 3.8% on and 96.2% off.
The current limit of the device is porportional to the voltage on
the SS pin until it reaches 1 V. When the voltage on the SS pin
reaches 1 V the current limit reaches the normal operating
condition of V SENSE = 50 mV. The voltage on the SS pin
continues to rise past the 1 V level with no effect on the current
limit. The reference voltage for the GATE linear control
amplifier is derived from the soft start voltage, such that the
inrush linear current limit is defined as
I LIMIT = V SS /(20 × R SENSE )
This provides a limit of 50 mV across R SENSE when V SS is at 1 V.
Therefore, the value for the SS capacitor is chosen as follows:
C SS = I SS × t
where I SS = 10 μA and t is the time required for the current limit
to ramp up.
Rev. A | Page 13 of 16
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